1. Field of the Invention
The present invention relates to a conductive structure, a layout structure including conductive structure, and a method for manufacturing conductive structure, and more particularly, to a method including planarization process and the conductive structure and the layout structure formed by the method.
2. Description of the Prior Art
The semiconductor integrated circuit (IC) industry has experienced rapid growth. And new microfabrication techniques are being developed with the realization of higher integration degrees and higher operation speeds. Chemical-mechanical polishing (hereinafter abbreviated as CMP) method is one such technique that is applied to planarization of interlayer insulating films, formation of contact plugs, and formation of embedded wiring in IC manufacturing process.
Typically, excess portions other than required metal or insulating material are removed by CMP and thus an even surface is obtained for subsequent processes. For example, in the interconnection fabrication process, series of trenches, openings, or vias are formed in an insulating material on a substrate and filled up with a conductive layer. And excess portions of the conductive layer are removed by the CMP. Consequently, wirings and/or via structures are formed in the insulating material. Those skilled in the art also know that CMP is also involved in planarization of shallow trench isolation region.
It is found that when removing the metal materials by the planarization, the unwanted short circuit may be formed between individual devices because of remnant metals left by the insufficient planarization. Furthermore, dishing defect, which is the formation of topographical defects, such as concavities or depressions, in the metal and metal alloy layer of features formed on the substrate surface, is often found. Dishing defect further results in a non-planar surface that impairs the ability to print high resolution lines during subsequent photolithographic steps and detrimentally affects subsequent surface topography of the substrate and device/line formation. Furthermore, dishing defect also detrimentally affects the performance of devices by lowering the conductance and increasing the resistance of the devices. Therefore, a method that is able to prevent aforementioned insufficient planarization and dishing defect is still in need.